Please be patient while the object screen loads.
Add to Quick Collection
- A real-time reconfigurable pipelined architecture with advanced power management for UTRA-FDD
- Stojcevski, A.
- Faulkner, Mike.
- Zayegh, A.
- Singh, Jugdutt.
- Veljanovski, R.
- Personal Indoor Mobile Radio Communication Conference (14th : 2003 : Beijing, China)
- 100606 Processor Architectures
- 1006 (four-digit-FOR)
- [S.l.] : Institute of Electrical and Electronics Engineers (IEEE),
- Digital Object ID
- 5 p. (p. 64-68).
- Open Access. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of La Trobe University's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to email@example.com
- By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
- This paper was reprinted from the Proceedings on 14th IEEE Personal Indoor Mobile Radio Communication Conference, pp. 64-68 and may be found at http://dx.doi.org/10.1109/PIMRC.2003.1264233
- Copyright (2003) IEEE
- conference paper
- Proceedings on 14th IEEE Personal Indoor Mobile Radio Communication Conference (PIMRC 2003), 1: 64-68